1. Technical Field
The invention disclosed broadly relates to memory technology and more particularly relates to memory chip powered-down glitch protection.
2. Background Art
Many VLSI products require on-chip receivers (OCR) that are powered-down when the chip is inactive. This means that the output of the OCR is forced into an inactive state and that the chip input pad is isolated from the internal operational nodes of the VLSI chip. This prevents the input pad from switching internal nodes on the chip and thereby eliminates power dissipation in a standby state, or when the chip is deactivated. Usually, this means that the output node or nodes are forced low (assuming positive logic). In many cases, the OCRs generate true and complement outputs from a given input signal both of which must be forced inactive. In addition, the input pad of the OCR must be completely isolated from any potential switching circuitry on the VLSI chip. Additional problems arise in the operation of powered-down OCRs when the chip comes from this powered-down (inactive) state to a powered-up (active) state. Potentially, the input to the chip can glitch, that is bounce from one logic state to another, if the timing between the activation signal and the OCR input pad signal is not carefully designed into the OCR.
Typically, signal timing is accomplished by delaying the chip select signal for some finite amount of time to allow the incoming signal to set up to the desired state. The incoming signal is enabled at a later stage by combination with the delayed chip enable signal. However, this requires the device to become dependent upon a delay circuit in order to insure proper operation and, in addition, increases the access time by the amount of time the chip select signal is delayed. The delay must be longer by a specified design margin to aid in reproducibility of the device. In a typical high speed application, this delay time can be on the order of five nanoseconds, which is significant compared to today's 40 nanoseconds or less required access time requirements.
Other problems arise from the case when the chip select signal delay is not properly designed and the input potential bounces from one logic state to another on the chip side of the OCR. In certain applications, this bouncing can degrade performance of the VLSI chip in question. For instance, in a static random access memory (SRAM), internal clocking pulses for the device are generated whenever the SRAM sees an input change state. When it sees a change, the chip clock begins to run and an access occurs. However, if a second input change occurs, then the chip must either abort the present access from the previous change, or continue with the present access and adjust for the new access specified. Aborting the present access for the address transition detection is very difficult to perform. Continuing the present access and adjusting for the new access specified is simpler, but increases access time by the fact there are certain clocking pulses generated by the input change that must take place before any access can begin. When two successive changes occur, there is a chance that these two clocking pulses cannot be simultaneous and will create either two distinct pulses or one long pulse to initiate the access operation. In either case, the access time is degraded by the bouncing of the inputs.
The prior art circuit of FIG. 1 relies, as shown, on a delay block 28 to delay the chip enable signal. In normal operation, chip select (CS) is low and the OCR operates by feeding the input signal through the true/complement signal generating AND circuitry 30 and 32 with the active, delayed chip select signal. In the power-down state, CS goes high which turns off devices 10 and 16, isolating the input pad from the chip. It is when the OCR comes out of this power-down state that is critical.
When the OCR comes out of the power-down (standby) state, CS transitions from a high to a low (active) level. CSB and CST are then generated immediately from devices 18 through 22 CSB and CST turn on devices 10 and 16 which allow the input signal from the OCR to reach node 100. This signal reaches the inputs to the true/complement generating AND gates 30 and 32. However, the outputs true and complement stay low until the delayed CS signal reaches the AND gates to enable them. When the delayed CS signal reaches the AND gates, the signals are then allowed to enter the device to start a memory access.
Problems with the prior art design become evident in this mode of operation. A CS delay circuit is necessary to delay the CS signal prior to enabling the output signals. The circuit must track along with any delay inside the circuit that runs in parallel to it. This also means that the delay must be long enough to provide a comfortable design margin, otherwise a potential glitching event can occur. Because the introduced delay in the CS signal must provide a comfortable design margin, the access time of the device will be increased. This is due to the fact that the access cannot begin until the signal passes the CS enabling point and enters the device for operation. The delay must be longer than the normal path to prevent glitching, therefore increasing the access time.
Because the normal path through the OCR runs in parallel with the CS delay circuit, there exists a race condition between the two signals to the AND gates for the logical combination. This race condition can cause glitching of the outputs if the CS signal reaches the AND gate before the signal from the chip input pad. Both outputs from the circuitry can both be in an on state for a brief period of time when the input signal switches. When the input rests at one logic state, then one of the two outputs sits high while the other sits low. If the input now switches to the other logic, then possibly the off output can go on before the on output turns off.
The circuit described in the present invention illustrates a new OCR design that contains a powered-down feature while providing non-glitching output signals with the added feature of guaranteed non-overlapping true and complement output signals. That is, the output will not glitch (or bounce) on the power operation which provides for single switching outputs that therefore would generate only one internal clocking pulse in the case of a SRAM operation application. In addition, it should be pointed out that this idea is not restricted to a true/complement OCR. Either side may be used to select a single sided OCR.